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multichannel ism band fsk/gfsk/ook/gook/ask transmitter adf7012 rev. 0 in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . specifications subjec t to chan g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features single-chip, low power uhf t r ansmitter 75 mhz to 1 g h z freq uency operation multichannel o p eration using frac-n pll 2.3 v to 3.6 v operation on-board regulatorstable performance programmable output power: ? 16 db m to +1 4 db m, 0.4 db s t eps data rat e s: dc t o 179.2 kbps low cu rrent co nsu m ption: 868 mh z, 10 d b m, 21 ma 433 mh z, 10 d b m, 17 ma 315 mh z, 0 dbm, 10 ma programmable low battery voltage indicator 24-lea d tssop applic a t io ns low cost wirel e ss dat a transf er security s y ste m s rf remote controls w i r e l e s s me t e ri n g secure ke yless entry general description the ad f7012 is a lo w p o w e r fs k/gfs k /o ok/go o k/as k uhf tra n smi t te r desig n e d fo r s h o r t ra n g e de v i ces (s rd s). th e o u t p ut p o w e r , ou t p ut cha n nels, de v i a t io n f r e q uen c y , an d mo d- u l a t ion typ e a r e p r og ra mma b l e b y usin g fo ur , 32-b i t r e g i s t ers. the f r ac t i o n al- n p ll and v c o w i t h ext e r n al ind u c t o r enab le t h e us er t o s e le c t a n y f r e q uen c y in t h e 75 m h z to 1 gh z b a nd . the fas t lo ck t i m e s o f t h e f r ac t i o n al- n p ll ma k e t h e ad f701 2 s u i t ab le in fast f r e q uen c y h o p p in g sys t em s. th e f i n e f r e q ue n c y de v i a t io n s a v a i l a b l e an d p ll phas e n o is e p e r f o r ma n c e f a ci li t a tes na r r o w -b an d op er a t ion. ther e a r e f i v e s e le c t ab le m o d u l a t i o n s c h e m e s: b i na r y f r e q uen c y s h i f t k e yin g (fs k ), ga us si a n f r eq uen c y s h i f t k e yi n g (gfs k ) , b i na r y o n -o f f k e y i ng (o ok), g a ussian o n -o f f k e y i ng (go o k), a nd a m p l i t ude shif t k e yin g (as k ). i n t h e co m p en sa tio n r e gis t er , t h e ou t p u t can b e m o ve d i n <1 p p m steps s o t h a t i ndir e c t com- p e ns a t i o n f o r f r e q u e nc y e r ror i n t h e c r y s t a l re f e re nc e c a n b e made. a sim p le 3 - w i r e in t e r f ace co n t rols t h e r e g i s t ers. i n p o w e r - do wn, t h e p a r t has a ty p i ca l q u ies c e n t c u r r en t o f <0.1 a. func ti on a l bl ock di a g r a m serial interface frequency compensation center frequency osc1 osc2 l1 l2 c vco clk out cpv dd cp gnd c reg printed inductor a gnd ce le data clk txdata txclk muxout rf gnd r set rf out c reg v dd d gnd dv dd fsk\gfsk ook\ask ook\ask clk r pfd/ charge pump - ? +fractional n vco pll lock detect muxout ldo regulator battery monitor pa 04617-0-001 fi g u r e 1 .
adf7012 rev. 0 | page 2 of 28 table of contents specifications ..................................................................................... 3 timing characteristics ..................................................................... 5 absolute maximum ratings ............................................................ 6 transistor count ........................................................................... 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 315 mhz ........................................................................................ 8 433 mhz ........................................................................................ 9 868 mhz ...................................................................................... 10 915 mhz ...................................................................................... 11 circuit description ......................................................................... 12 pll operation ............................................................................ 12 crystal oscillator ........................................................................ 12 crystal compensation register ................................................ 12 clock out circuit ....................................................................... 12 loop filter ................................................................................... 13 volt age- c ont rol le d os ci l lator ( vc o) ..................................... 13 volt age regu l ators ...................................................................... 13 fsk modulation .......................................................................... 13 gfsk modulation ...................................................................... 14 power amplifier .......................................................................... 14 gook modulation .................................................................... 15 output divider ........................................................................... 16 muxout modes ....................................................................... 16 theory of operation ...................................................................... 17 choosing the external inductor value .................................... 17 choosing the crystal/pfd value ............................................. 17 tips on designing the loop filter ........................................... 17 pa matching ................................................................................ 18 transmit protocol and coding considerations ..................... 18 application examples .................................................................... 19 315 mhz operation ................................................................... 20 433 mhz operation ................................................................... 21 868 mhz operation ................................................................... 22 915 mhz operation ................................................................... 23 register descriptions ..................................................................... 24 r register ..................................................................................... 24 n-counter latch ........................................................................ 25 modulation register .................................................................. 26 function register ....................................................................... 27 outline dimensions ....................................................................... 28 ordering guide .......................................................................... 28 revision history 10/04revision 0: initial version
adf7012 rev. 0 | page 3 of 28 specifications dv dd = 2.3 v C 3.6 v; agnd = dgnd = 0 v; t a = t min to t max , unless otherwise noted. operating temperature range is ?40c to +85c. table 1. parameter b version unit conditions/comments rf output characteristics operating frequency 75/1000 mhz min/max vco range adjustable using external inductor; divide-by-2, -4, -8 options may be required phase frequency detector f rf /128 hz min modulation parameters data rate fsk/gfsk 179.2 kbps using 1 mhz loop bandwidth data rate ask/ook 64 kbps based on us fcc 15.247 specfications for acp; higher data rates are achievable depending on local regulations deviation fsk/gfsk pfd/2 14 hz min for example, 10 mhz pfd C deviation min = 610 hz 511 pfd/2 14 hz max for example, 10 mhz pfd C deviation max = 311.7 khz gfsk bt 0.5 typ ask modulation depth 25 db max ook feedthrough (pa off) ?40 dbm typ f rf = fvco ?80 dbm typ f rf = fvco/2 power amplifier parameters max power setting, dv dd = 3.6 v 14 dbm f rf = 915 mhz, pa is matched into 50 ? max power setting, dv dd = 3.0 v 13.5 dbm f rf = 915 mhz, pa is matched into 50 ? max power setting, dv dd = 2.3 v 12.5 dbm f rf = 915 mhz, pa is matched into 50 ? max power setting, dv dd = 3.6 v 14.5 dbm f rf = 433 mhz, pa is matched into 50 ? max power setting, dv dd = 3.0 v 14 dbm f rf = 433 mhz, pa is matched into 50 ? max power setting, dv dd = 2.3 v 13 dbm f rf = 433 mhz, pa is matched into 50 ? pa programmability 0.4 db typ pa output = ?20 dbm to +13 dbm power supplies dv dd 2.3/3.6 v min/v max current comsumption 315 mhz, 0 dbm/5 dbm 8/14 ma typ dv dd = 3.0 v, pa is matched into 50 ?, ivco = min 433 mhz, 0 dbm/10 dbm 10/18 ma typ 868 mhz, 0 dbm/10 dbm/14 dbm 14/21/32 ma typ 915 mhz, 0 dbm/10 dbm/14 dbm 16/24/35 ma typ vco current consumption 1/8 ma min/max vco current consumption is programmable crystal oscillator current consumption 190 a typ regulator current consumption 280 a typ power-down current 0.1/1 a typ/max reference input crystal reference frequency 3.4/26 mhz min/max single-ended reference frequ ency 3.4/26 mhz min/max crystal power-on time 3.4 mhz/26 mhz 1.8/2.2 ms typ ce to clock enable valid single-ended input level cmos levels refer to the logic inputs parameter. applied to osc 2 C oscillator circuit disabled.
adf7012 rev. 0 | page 4 of 28 parameter b version unit conditions/comments phase-locked loop parameters vco gain 315mhz 22 mhz/v typ vco divide-by-2 active 433mhz 24 mhz/v typ vco divide-by-2 active 868mhz 80 mhz/v typ 915mhz 88 mhz/v typ vco tuning range 0.3/2.0 v min/max spurious (ivco min/ max) ?65/?70 dbc i vco is programmable charge pump current setting [00] 0.3 ma typ refering to db[7:6] in function register setting [01] 0.9 ma typ refering to db[7:6] in function register setting [10] 1.5 ma typ refering to db[7:6] in function register setting [11] 2.1 ma typ refering to db[7:6] in function register phase noise (in band) 1 315mhz ?85 dbc/hz typ pfd = 10 mhz, 5 khz offset, i vco = 2 ma 433mhz ?83 dbc/hz typ pfd = 10 mhz, 5 khz offset, i vco = 2 ma 868mhz ?80 dbc/hz typ pfd = 10 mhz, 5 khz offset, i vco = 3 ma 915mhz ?80 dbc/hz typ pfd = 10 mhz, 5 khz offset, i vco = 3 ma phase noise (out of band) 1 315mhz ?103 dbc/hz typ pfd = 10 mhz, 1 mhz offset, i vco = 2 ma 433mhz ?104 dbc/hz typ pfd = 10 mhz, 1 mhz offset, i vco = 2 ma 868mhz ?115 dbc/hz typ pfd = 10 mhz, 1 mhz offset, i vco = 3 ma 915mhz ?114 dbc/hz typ pfd = 10 mhz, 1 mhz offset, i vco = 3 ma harmonic content (second) 2 ?20 dbc typ f rf = f vco harmonic content (third) 2 ?30 dbc typ harmonic content (others) 2 ?27 dbc typ harmonic content (second) 2 ?24 dbc typ f rf = f vco /n (where n = 2, 4, 8) harmonic content (third) 2 ?14 dbc typ harmonic content (others) 2 ?19 dbc typ logic inputs input high voltage,v inh 0.7 dv dd v min input low voltage, v inl 0.2 dv dd v max input current, i inh /i inl 1 a max input capacitance, c in 4.0 pf max logic outputs output high voltage, v oh dv dd ? 0.4 v min cmos output chosen output high current, i oh , 500 a max output low voltage, v ol 0.4 v max i ol = 500 a 1 measurements made with n frac = 2048. 2 measurements made without harmonic filter.
adf7012 rev. 0 | page 5 of 2 8 timing characteristics dv dd = 3 v 10% ; a g nd = d g nd = 0 v ; t a = t min to t max , u n l e ss ot he r w i s e no te d. table 2. parameter limit at t min to t ma x (b version ) unit test condition s /comments t 1 20 ns min le setup time t 2 10 ns min data-to-cloc k se tup time t 3 10 ns min data-to-cloc k h o ld time t 4 25 ns min clock hig h duration t 5 25 ns min clock l o w duration t 6 10 ns min clock Cto-le set u p time t 7 20 ns min le pulse width cloc k data le le db23 (msb) db22 db2 db1 (control bit c2) db0 (lsb) (control bit c1) t 1 t 2 t 3 t 7 t 6 t 4 t 5 04617-0-002 f i g u re 2. ti ming d i ag r a m
adf7012 rev. 0 | page 6 of 2 8 absolute maximum ratings t a = 2 5 c , u n l e ss ot he r w i s e no t e d. table 3. p a r a m e t e r r a t i n g dv dd to gnd ( g nd = agnd = dgnd = 0 v) ?0.3 v to +3.9 v digital i/o voltage to gnd ?0.3 v to dv dd + 0.3 v analog i/o voltage to gnd ?0.3 v to dv dd + 0.3 v operating tem p erature range maximum junction temperature 150c tssop ja thermal impedance 150.4c/w lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c s t r e s s es a b o v e t h os e list e d u nde r a b s o l u te m a xim u m r a t i n g s ma y ca us e p e r m a n e n t dama ge to t h e de vi ce. t h is is a st r e ss r a t i ng on ly ; f u n c t i on a l op e r at i o n of t h e d e v i c e a t t h e s e or an y o t h e r con d i t ions a b o v e t h os e list e d i n t h e op era t io nal s e c t ion s o f t h is sp e c if ic a t io n is n o t i m pli e d . e x p o sur e t o a b s o l u t e max i m u m r a t i ng co ndi t i on s fo r ex tende d p e r i o d s ma y a f fe c t de vice rel i a b i l i t y . this d e vice is a hig h p e r f o r ma nce rf in t e g r a t e d cir c ui t w i t h an es d ra ting o f 1 kv an d i t is es d s e n s i t i v e . p r op er p r eca u tion s sh o u l d b e t a ken fo r ha n d lin g and ass e m b ly . transis t o r count 35819 (cm o s) esd caution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
adf7012 rev. 0 | page 7 of 2 8 pin conf iguration and fu nction descriptions adf7012 top view (not to scale) dv dd 1 c reg1 2 cp out 3 txdata 4 txclk 5 c reg2 r set agnd dv dd rf out 24 23 22 21 20 muxout 6 dgnd 7 osc1 8 osc2 9 rf gnd vco in c vco l2 19 18 17 16 clk out 10 clk 11 l1 ce 15 14 data 12 le tssop 13 04617- 0 - 0 03 fi g u r e 3 . ta ble 4. pi n f u nct i ona l des c ri pt i o ns pin no. mnemonic description 1 d v dd positive supply for the digital circuitry. this mus t be between 2. 3 v and 3.6 v. d e coupling capacitors to the analog ground plane sh ould be placed as clo s e as pos si ble to this pin. 2 c reg1 a 2.2 f capacitor should be ad ded at c reg to reduce regulator noise and imp ro ve stability. a reduced capacitor improve s regulator power-on time, but may cause higher spurious noise. 3 c p ou t charge pump output. t h is output generates current pulses that are integrated in the loop filter. t h e integrated current changes the control voltage on the inpu t to the vco. 4 tx data digital data to be tran smitted is inputted on this pin. 5 t x c l k gfsk and gook only. t h is cloc k output is used to sync hronize microcontroller data to the tx d a ta pin of the adf7012. the clock is pr ovided at the same frequency as the data rate. the microco ntroller upd a tes txdata on the falling edge of txclk. the rising edge of txc l k is used to sample txdata at the midpoint of each bit. 6 m u x o u t provides the lock_detect signal. this determines if the pll is locked to th e correct frequency and also monitors battery voltage. other signal s in clud e regulator_read y, whic h indicates the status of th e serial i n terface regulator. 7 dgnd ground for digital section. 8 osc1 t h e reference cr ystal should be connected betw een this pin a n d osc2. 9 o s c 2 the reference cr ystal should be connected between this pin and osc1. a tcxo r e ference may be used, by driving this pin with cmos levels, and p o wering do wn t h e crystal oscilla t or bit in softwa re. 1 0 c l k ou t a divided-down version of the crystal reference with outp ut driv er. the digital clock o utput may be used to drive severa l other c m os inputs, such as a micro con t rolle r clock. th e output has a 50:50 mark-sp a ce ratio. 1 1 c l k se ria l cl oc k in put. th is s e ria l c l oc k is used to clock in the serial data to the registers. the data is latched into the 32-bit shift register on the clk rising edge. this input is a high impedance cmos input. 1 2 d a t a serial data inpu t. the serial data is loaded msb first with the two lsbs be ing the c o ntrol bits. this is a high impedance cm os input. 1 3 l e load enable, c m os input. when le goes high, the data stored in the shift regi sters is lo aded into one of the four latches, the latch being select ed using the control bits. 1 4 c e chip enable. bri n ging ce low pu ts the adf7012 i n to comp lete power-down, drawing < 1ua. reg i ster values are lost whe n ce is l o w and the part must be reprogrammed once c e is brought high. 1 5 l 1 connected to ex ternal printed or disc rete inductor. see choosi n g the external inductor value for advice on the value of the inductor to be con n ected between l1 and l2. 16 l2 connected to external pr inted or dis c rete inductor. 1 7 c vco a 220 nf capacitor should be tie d between the c vco and c reg2 pi ns. this line should run underne a th the adf701 2. this capacitor is necessary to ensure stable vco operatio n . 1 8 v c o in the tuning voltage on this pin deter mines the output freq uency of the volt age controlled osc i llator (vco). the higher the tuning voltage, the higher the output freq uency. 1 9 r f gn d ground for output stage of t r a n smitter. 2 0 r f ou t the modulated signal i s avai lab l e at this pin. output power levels are from C16 dbm to +12 dbm. the output should be impe d ance matched using suitable c o mpon ents to the desired load. see the pa matc hing section. 2 1 d v dd voltage supply f o r vco and pa section. t h is sh o u ld have the sa me supply as d v dd pin 1, and should be between 2.3 v and 3.6 v. place decoupli ng capa citors to the analog ground plane as c l ose a s p o s s i bl e to th is p i n . 22 agnd ground pin for t h e rf analog circuitry. 2 3 r set external resi sto r to set charge p u mp current and some internal bias currents. use 3.6 kv as default. 2 4 c reg2 add a 470 nf ca pacitor at c reg t o reduce regulator noise and im prove sta b ility. a reduced capacitor improve s regulator power -on time and ph ase noi s e, but may have stabi l ity issues over th e supply and temperature.
adf7012 rev. 0 | page 8 of 2 8 typical perf orm ance cha r acte ristics 315 mhz phase noise (hz) dbc (hz) ?6 0 ?7 0 ?8 0 ?9 0 ?100 ?110 ?120 ?130 ?140 1.0k 10.0k 100.0k 1.0m 10.0m 04617-0-004 = normal frequency = 9.08 khz level = ? 84.47dbc/hz f i gure 4. p h ase n o i s e r e spons e dv dd = 3 . 0 v , i cp = 0.8 6 ma iv c o = 2. 0 ma, f ou t = 31 5 m h z, pfd = 3.6 8 64 m h z , p a b i a s = 5. 5 ma 5 ?20 ?10 0 ?50 ?40 ?30 ?70 ?80 ?90 ?60 ?95 04617-0-005 1ma 2 1 center 315mhz 50khz/ span 500khz ref lvl 5dbm 0.45dbm 315.05060120mhz 30db dbm rf att unit 5khz 5khz 500ms rbw vbw swt a f i gure 5 . fsk m o dul a tio n , p o wer = 0 d b m , d a ta ra te = 1 k bps , f de vi a t ion = 5 0 khz 5 ?20 ?10 0 ?50 ?40 ?30 ?70 ?80 ?90 ?60 ?95 04617-0-006 1ma 1 center 315mhz 40mhz/ d1 ?41.5dbm d2 ?49dbm span 400mhz ref lvl 5dbm 0.31dbm 315.40080160mhz 30db dbm rf att unit 500khz 500khz 5ms rbw vbw swt a 1 [t1] 0.31dbm 315.40080160mhz f i gure 6 . spurio us c o m p o n ents meets f c c sp ecs 5 ?20 ?10 0 ?50 ?40 ?30 ?70 ?80 ?90 ?60 ?95 04617-0-007 1ma 1 center 3.5mhz 700mhz/ d1 ?41.5dbm span 7ghz ref lvl 5dbm 0.27dbm 308.61723447mhz 30db dbm rf att unit 1mhz 1mhz 17.5ms rbw vbw swt a 3 2 4 2 [t1] 1 [t1] 0.27dbm 308.61723447mhz ?35.43dbm 631.26252505mhz 3 [t1] 4 [t1] ?11.48dbm 939.87975952mhz ?34.11dbm 1.26252505ghz f i gure 7. ha rm on ic r e s p ons e , r f ou t m a tch e d t o 50 ?, no f ilt er 5 ?20 ?10 0 ?50 ?40 ?30 ?70 ?80 ?90 ?60 ?95 04617-0-008 1ma sgl 1 center 3.5mhz 700mhz/ d1 ?41.5dbm span 7ghz ref lvl 5dbm 0.18dbm 308.61723447mhz 30db dbm rf att unit 1mhz 1mhz 17.5ms rbw vbw swt a 3 2 4 2 [t1] 1 [t1] 0.18dbm 308.61723447mhz ?50.53dbm 631.26252505mhz 3 [t1] 4 [t1] ?42.93dbm 939.87975952mhz ?55.48dbm 1.26252505ghz f i gure 8. ha rm on ic r e s p ons e , f i f t h- o r der butter w or th f i l t er 5 ?20 ?10 0 ?50 ?40 ?30 ?70 ?80 ?90 ?60 ?95 04617-0-009 1ma 1 2 3 center 315mhz 50khz/ span 500khz ref lvl 5dbm 20.33dbm 26.55310621khz 30db dbm rf att unit 5khz 5khz 500ms rbw vbw swt a 3 [t1] 2 [t1] 1 [t1] ?3.49dbm 315.00012525mhz ? 20.33db 26.55310621khz ? 20.85db ? 27.55511022khz f i g u re 9. o o k m o d u lat i on, p o wer = 0 dbm, d a t a r a t e = 10 k bps
adf7012 rev. 0 | page 9 of 2 8 433 mhz 04617-0-010 1 2.00v/ 2 1 2 1.00v/ 1.50ms 720mv 500 s trig'd 1 clkout ce f i g u re 10. cr y s t a l p o wer - o n ti m e , 4 m h z, ti me = 1. 6 ms phase noise (hz) dbc (hz) ?4 0 ?6 0 ?8 0 ?100 ?120 ?140 ?160 ?180 ?200 1.0k 10.0k 100.0k 1.0m 10.0m 04617-0-011 = normal frequency = 393.38 khz level = ? 102.34dbc/hz f i g u re 11. phas e n o is e r e s p ons e i cp = 2. 0 ma, i vc o = 2.0 ma, rf ou t = 43 3.92 m h z , p f d = 4 m h z , p a bi a s = 5 . 5 m a 15 ?10 0 10 ?40 ?30 ?20 ?60 ?70 ?80 ?50 ?85 04617-0-012 1ma 1 start 433.05mhz 174khz/ stop 434.79khz ref lvl 15dbm 5.60dbm 433.91158317mhz 40db dbm rf att unit 10khz 300khz 44ms rbw vbw swt a d1 ?36dbm f i gure 12. fsk mod u lat i on, p o w e r = 10 db m, d a t a rat e = 38. 4 k bps , f de vi a t io n = 1 9.28 kh z 15 ?10 0 10 ?40 ?30 ?20 ?60 ?70 ?80 ?50 ?85 04617- 0- 013 1ma 1 center 433.9500601mhz 3.2mhz/ span 32mhz ref lvl 15dbm 10.01dbm 433.91158317mhz 40db dbm rf att unit 30khz 30khz 90ms rbw vbw swt a d1 ? 36dbm f i gure 13. spur ious c o mp onentsme e ts et si sp e c s 15 ?10 0 10 ?40 ?30 ?20 ?60 ?70 ?80 ?50 ?85 04617-0-014 1ma 1 center 3.5ghz 700mhz/ span 7ghz ref lvl 15dbm 10.10dbm 434.86973948mhz 40db dbm rf att unit 1mhz 1mhz 17.5ms rbw vbw swt a d1 ?36dbm d1 ?30dbm 2 3 4 2 [t1] 1 [t1] 10.10dbm 434.86973948mhz ?15.25dbm 869.73947896mhz 3 [t1] 4 [t1] ?5.12dbm 1.30460922ghz ?17.57dbm 1.73947896ghz f i gur e 1 4 . ha rm onic re sp o n s e , rf ou t ma t c h e d to 5 0 ? , n o f ilt er 15 ?10 0 10 ?40 ?30 ?20 ?60 ?70 ?80 ?50 ?85 04617-0-015 1ma sgl 1 center 3.5ghz 700mhz/ span 7ghz ref lvl 15dbm 9.51dbm 434.86973948mhz 40db dbm rf att unit 1mhz 1mhz 17.5ms rbw vbw swt a d1 ?36dbm d1 ?30dbm 2 3 4 2 [t1] 1 [t1] 9.51dbm 434.86973948mhz ?33.75dbm 869.73947896mhz 3 [t1] 4 [t1] ?43.60dbm 1.30460922ghz ?43.44dbm 1.73947896ghz f i gure 15. har m onic resp ons e , f i f t h- o r der butter w o r t h f i lte r
adf7012 rev. 0 | page 10 of 28 868 mhz phase noise (hz) dbc (hz) 0 ?2 0 ?4 0 ?6 0 ?8 0 ?100 ?120 ?140 ?160 1.0k 10.0k 100.0k 1.0m 10.0m 04617-0-016 = normal frequency = 251.3 khz level = ? 99.39dbc/hz f i g u re 16. phas e n o is e r e s p ons e Ci cp = 2. 5 ma, i vc o = 1.4 4 ma, r f ou t = 8 68. 9 5 m h z, pfd = 4.9 1 52 m h z, p o wer = 12. 5 dbm, p a bi as = m a x 15 ?10 0 10 ?40 ?30 ?20 ?60 ?70 ?80 ?50 ?85 04617-0-017 1ma ln center 868.944489mhz 60khz/ span 600khz ref lvl 15dbm ? 40.44dbm 869.20000000mhz 30db ?20dbm dbm rf att mixer unit 10khz 10khz 15ms rbw vbw swt a d2 ? 36dbm 1 2 2 [t1] 1 [t1] 40.44dbm 869.20000000mhz 8.02dbm 868.96673347mhz 1max f i g u re 17. fsk m o d u lat i on, p o wer = 1 2 .5 db m, d a t a r a te = 38. 4 k bps, f de vi a t ion = 19. 2 k h z 15 ?10 0 10 ?40 ?30 ?20 ?60 ?70 ?80 ?50 ?85 04617-0-018 1ma ln start 856.5mhz 2.5mhz/ stop 881.5mhz ref lvl 15dbm 12.55dbm 869.025050100mhz 30db ?20dbm dbm rf att mixer unit 2khz 2khz 16s rbw vbw swt a d2 ?36dbm d1 ?54dbm 1 2 3 1max 2 [t1] 3 [t1] 1 [t1] 12.55dbm 869.02505010mhz ? 57.89dbm 859.16695500mhz ? 81.97dbm 862.00000000mhz f i gure 18. spur ious c o mp onentsme e ts et si sp e c s 15 ?10 0 10 ?40 ?30 ?20 ?60 ?70 ?80 ?50 ?85 04617-0-019 1ma 1 center 3.8ghz 640mhz/ span 6.4ghz ref lvl 15dbm 12.27dbm 869.33867735mhz 40db dbm rf att unit 1mhz 1mhz 16ms rbw vbw swt a d1 ?30dbm 2 3 4 2 [t1] 1 [t1] 12.27dbm 869.33867735mhz ?4.00dbm 1.72865731ghz 3 [t1] 4 [t1] ?16.88dbm 2.59699399ghz ?15.06dbm 3.46913828ghz 1max f i gur e 1 9 . ha rm onic re sp o n s e , rf ou t ma t c h e d to 5 0 ? , n o f ilt er 15 ?10 0 10 ?40 ?30 ?20 ?60 ?70 ?80 ?50 ?85 04617-0-020 1ma ln start 3.8ghz 640mhz/ span 6.4ghz ref lvl 15dbm 10.39dbm 869.33867735mhz 30db ?20dbm dbm rf att mixer unit 1khz 1khz 10ms rbw vbw swt a d2 ?30dbm 1 2 3 1max 3 [t1] 2 [t1] 1 [t1] 10.39dbm 869.33867735mhz ? 50.92dbm 1.72000000ghz ? 50.40dbm 2.59600000ghz f i gur e 2 0 . ha rm on ic re sp o n s e , f i fth - or de r ch e b ysh e v f i l t e r
adf7012 rev. 0 | page 11 of 28 915 mhz phase noise (hz) dbc (hz) ?4 0 ?6 0 ?8 0 ?100 ?120 ?140 ?160 ?180 ?200 1.0k 10.0k 100.0k 1.0m 10.0m 04617-0-021 = normal frequency = 992.38 khz level = ? 102.34dbc/hz f i g u re 21. phas e n o is e r e s p ons e Ci cp = 1. 4 4 ma, i vc o = 3. 0 ma, r f ou t = 9 15. 2 mh z, pfd =1 0 m h z , p o wer = 10 dbm , p a b i as = 5.5 ma 15 ?10 0 10 ?40 ?30 ?20 ?60 ?70 ?80 ?50 ?85 04617-0-036 1ma center 915.190982mhz 50khz/ span 500khz ref lvl 15dbm 3.88dbm 915.19098196mhz 40db dbm rf att unit 10khz 300khz 15ms rbw vbw swt a 1 1max f i gure 22. fsk mod u lat i on, p o w e r = 10 db m, d a t a rat e = 38. 4 k bps , f d ev iat i on = 1 9. 2 kh z 15 ?10 0 10 ?40 ?30 ?20 ?60 ?70 ?80 ?50 ?85 04617-0-037 1ma sgl center 915.2mhz 40mhz/ span 400mhz ref lvl 15dbm 9.94dbm 915.23167977mhz 40db dbm rf att unit 10khz 300khz 100ms rbw vbw swt a * 1 d1 ?49.5dbm d1 ?41.5dbm f i gure 23. spur ious co mpo n entsme e ts fc c specs 15 ?10 0 10 ?40 ?30 ?20 ?60 ?70 ?80 ?50 ?85 04617-0-038 1ma 1 center 3.8ghz 640mhz/ span 6.4ghz ref lvl 15dbm 10.25dbm 907.81563126mhz 40db dbm rf att unit 50mhz 50mhz 6.4s rbw vbw swt a d1 ?41.5dbm 2 3 4 2 [t1] 1 [t1] 10.25dbm 907.81563126mhz ?10.06dbm 1.83126253ghz 3 [t1] 4 [t1] ?20.29dbm 2.74188377ghz ?17.50dbm 3.65250501ghz 1max f i gur e 2 4 . ha rm onic re sp o n s e , rf ou t ma t c h e d to 5 0 ? , n o f ilt er 15 ?10 0 10 ?40 ?30 ?20 ?60 ?70 ?80 ?50 ?85 04617-0-039 1ma 1 center 3.8ghz 640mhz/ span 6.4ghz ref lvl 15dbm 9.06dbm 907.81563126mhz 40db dbm rf att unit 50mhz 50mhz 6.4s rbw vbw swt a d1 ?41.5dbm 2 3 4 2 [t1] 1 [t1] 9.06dbm 907.81563126mhz ?48.40dbm 1.83126253ghz 3 [t1] 4 [t1] ?46.22dbm 2.74188377ghz ?46.96dbm 3.65250501ghz 1max f i gur e 2 5 . ha rm on ic re sp o n s e , f i fth - or de r ch e b ysh e v f i l t e r
adf7012 rev. 0 | page 12 of 28 circuit description pll operation a f r a c ti o n al- n p ll allo w s m u l t i p le o u t p u t f r eq uen c i e s t o be g e n e ra t e d f r o m a sin g le -r efer ence os ci l l a t o r (us u al l y a cr ys t a l) sim p l y b y cha n g i n g t h e p r og ra mma b l e n va l u e fo un d in t h e n r e g i s t er . a t t h e phas e f r e q uen c y det e c t o r (p fd ), t h e r e fer e n c e i s co m p a r e d to a d i vi de d - do w n ve rsio n o f t h e o u tp u t f r e q uen c y (v co/n). i f v c o/n is t o o lo w a f r eq uen c y , typ i call y the o u t p u t f r e q uen c y is lo w e r t h a n des i r e d , an d t h e pf d a nd cha r ge-p u m p co m b ina t io n s e n d s addi t i o n a l c u r r en t p u ls es t o t h e lo o p f i l t er . t h i s in cr ea ses t h e v o l t a g e a p p l ied t o t h e in p u t o f th e v c o . b e ca us e t h e v c o o f th e ad f7012 has a p o si ti ve f r eq uen c y vs. volt age ch ar a c te r i st i c , a n y i n c r e a s e i n t h e v t u n e volt age a p pl i e d t o th e v c o i n p u t in cr ea se s t h e o u t p u t f r eq ue n c y a t a ra t e o f k v , t h e tu n i ng s e ns it iv i t y of t h e v c o ( m hz / v ) . a t e a ch i n te r v a l of 1/p f d s e con d s , a co m p a r is o n is made a t t h e pfd un t i l t h e p f d a nd cha r g e p u m p e v en t u al l y fo r c e a s t a t e o f e q u i lib r i u m i n t h e p ll w h er e p f d f r e q uen c y = v c o/ n. a t t h is p o in t, t h e p ll can be d e scri be d a s loc k ed . n r cp pfd crystal/r loop filter fvco vco vco/n 04617-0-022 f i g u re 26. n f r n f f pfd crystal out = = ( 1 ) fo r a fr a c t i o n a l n p l l ? ? ? ? ? ? + = frac int pfd out n n f f ( 2 ) w h er e n fra c can be b i ts m1 t o m12 in t h e f r ac tio n al n r e g i st er . crystal oscillator t h e on - b o a rd c r y s t a l o s c i l l a t or c i rc u i t r y ( f i g u r e 2 7 ) a l l o w s an inexp e n s i v e q u ar tz cr ys t a l t o b e us e d as t h e pll r e fer e n c e . th e os cil l a t o r cir c u i t is ena b le d b y s e t t in g x o eb lo w . i t is enab led b y defa u l t o n p o w e r - u p a nd is dis a b l e d b y b r in g i ng ce lo w . er r o rs in t h e cr ys t a l c a n b e co r r e c t e d usin g t h e er r o r co r r e c t i o n r e g i s t er w i t h in t h e r reg i s t er . a s i ng l e - e nd e d re fe re nc e m a y b e u s e d i n ste a d o f a c r y s t a l, b y a p p l ying a s q uar e wa v e t o the osc2 p i n, wi t h x o eb s e t hig h . os c 1 cp1 cp2 os c 2 04617-0-023 f i g u re 27. t w o pa r a ll e l r e s o n a n t ca pa c i t o r s a r e r e q u i r ed f o r osc i ll a t i o n a t t h e co r r e c t f r e q uen c yt h e val u e o f t h es e de p e nd o n t h e cr ys t a l sp e c if ic a t ion. t h e y sh o u l d b e ch os e n s o t h a t t h e s e r i es va l u e o f ca pa ci ta n c e ad ded t o t h e pcb tra c k ca pa ci ta n c e a d d s t o gi v e th e lo ad ca p a c i tan c e o f th e cr ys tal , us ual l y 20 pf . t r ac k ca p a c i tan c e va l u es va r y b e t w e e n 2 pf to 5 pf , dep e n d in g on b o a r d la yo u t . w h er e p o s s i b le , t o en s u r e s t a b le f r e q uen c y o p era t io n o v er al l co n d i ti o n s, ca pa ci t o r s sh o u ld b e c h osen so tha t th ey h a v e a v e r y lo w t e m p era t ure co ef f i cien t and/o r o p p o si te t e m p era t ur e co ef f i cien ts crystal compensation register the ad f7012 f e a t ur es a 15-b i t f i xed m o d u l u s, which al lo ws t h e o u t p u t f r eq ue n c y t o be ad j u s t ed in st eps o f fp fd/15. this f i ne r e s o l u tio n can b e us ed t o easil y co m p ens a te fo r ini t i a l er r o r a n d t e m p era t ur e dr i f t in t h e r e fer e nce cr ys t a l . f ad j u s t = f st e p fec (3) w h er e f st ep = fp fd/215 an d fe c = b i ts f1 t o f11 in t h e r r e gi s t e r . n o t e th a t th e n o ta t i o n i s t w o s c o m p l i m e n t , s o f 1 1 r e p r es en ts t h e sig n o f t h e fec n u m b er . ex a m ple f pf d = 10 mh z f ad j u s t = ?11 kh z f st e p = 10 mh z/2 15 = 305.176 h z fec = ?11 kh z/305.17 h z = ?36 = ?(00000100 100) = 11111011100 = 0x7d c clock ou t circuit the clo c k o u t ci r c ui t t a k e s t h e r e fer e n c e clo c k s i g n al f r o m t h e o s ci l l a t o r s e c t ion ab o v e and su pplies a d i v i de d- do wn 50:50 ma rk- s p a ce sig n a l to t h e cl k ou t p i n . an ev en d i v i de f r o m 2 t o 30 is a v a i lab l e . this divide is s e t b y t h e d b [19:22] in the r r e g i s t er . on p o w e r - u p , t h e cl k ou t defa u l ts t o divide b y 16. 04617-0-024 dv dd clk out enable bit clk out osc1 divider 1 to 15 2 f i g u re 28.
adf7012 rev. 0 | page 13 of 28 the o u t p u t b u f f er t o clk ou t i s e n a b led b y set t in g b i t d b 4 in t h e f u n c ti o n r e gi s t e r h i gh . o n po w e r - u p , t h i s b i t i s s e t h i gh . the o u t p u t b u f f er ca n dr iv e u p t o a 20 pf lo ad wi t h a 10% r i s e tim e a t 4.8 mh z. f a s t er edg e s c a n r e s u l t in s o me s p ur io us f eed th r o ugh t o th e o u t p u t . a sm all se ri e s r e si s t o r (50 ) ca n b e used t o s l o w t h e c l oc k ed g e s t o r e d u ce t h ese s p ur s a t f clk . loop filte r the lo o p f i l t er i n t e g r a t es t h e c u r r en t p u ls es f r o m t h e cha r g e p u m p t o fo r m a v o l t a g e t h a t t u nes t h e ou t p u t o f t h e v c o t o t h e desir e d f r e q uenc y . i t a l s o a t te n u a t es sp ur io us le vels gen e r a te d b y th e p ll. a typ i cal lo o p f i l t er desig n is sh o w n in f i gur e 29. 04617-0-025 charge pump out vco f i g u re 29. i n fs k, t h e lo op s h o u l d b e desig n e d s o tha t t h e lo o p ba ndwid t h (l b w ) i s a mi nim u m o f t w o t o th r e e tim e s t h e da ta ra t e . w i deni n g t h e l b w exces s i v e l y r e d u ces t h e t i me s p e n t j u m p in g be tw e e n f r e q uen c ies, b u t r e s u l t s in r e d u ce d sp ur io us a t t e n u a t io n. s e e t h e s e c t ion t i p s o n d e sig n in g t h e l o o p f i l t er . f o r o o k/as k sys t em s, a wid e r lo o p ba n d wid t h tha n f o r fs k sys t em s is desir a b l e . the s u dde n la rg e tra n si t i o n b e tw e e n tw o p o w e r le ve ls r e s u l t s in v c o p u l l in g (v c o t e m p o r a r il y g o es t o inco r r e c t f r e q uen c y ) a nd can ca us e a wider o u tp u t sp e c t r um. by widen i n g t h e lo o p b a ndwi d t h a m i ni m u m of 10 da t a r a te, v c o p u l l i n g is mini mi ze d b e c a us e t h e lo o p s e tt les q u ick l y b a ck t o th e co rr ect f r eq ue n c y . t h e f r ee d e s i gn t o o l ad i s i m p l l ? ca n be us e d t o desig n lo o p f i l t ers f o r th e ad i fa mil y o f tra n smi t t e rs. voltage-contr o lled oscillator ( v co) the ad f7012 f e a t ur es a n o n -chi p v c o wi t h an ext e r n al tank ind u c t o r , w h ich is us e d t o s e t t h e f r e q uen c y ra n g e . t h e ce n t er f r e q uen c y o f osci l l a t ion is go v e r n e d b y t h e in t e r n a l va rac t o r ca p a ci tan c e and tha t o f t h e ext e r n al ind u c t o r co m b in e d wi t h t h e b o n d - w ir e i n d u c t a n c e . an a p p r o x ima t ion fo r t h is is g i v e n in t h e eq u a ti o n 4 . f o r a m o r e ac cu ra t e se l e cti o n o f th e i n d u ct o r , see th e secti o n c h o o si n g th e ext e rn al i n d u ct o r v a l u e . ( ) fixed var ext int vco c c l l f + + = (4) the va rac t o r c a p a ci tan c e ca n b e ad j u s t e d in s o f t wa r e t o in cr eas e t h e ef fe c t i v e v c o ra n g e b y wr i t in g t o b i ts v a 1 a nd v a 2 i n t h e r r e g i ster . u nde r ty p i ca l condi t i o n s, s e t t i n g v a 1 a nd v a 2 hi g h in cr eas e s t h e cen t er f r eq uen c y b y r e d u cin g t h e va rac t o r ca p a ci tan c e b y a p p r o x ima t e l y 1. 3 pf . f i gur e 32 sh o w s t h e v c o gain o v er t e m p er a t ur e a nd f r e q uen c y . v c o ga in i s im po r t a n t in d e t e r m i n in g t h e loo p f i l t e r d e si gn p r e d ic t a b l e chan ges in v c o gain r e su l t i n g i n a cha n ge i n t h e lo o p f i l t er b a ndwi d t h can b e o f fs et b y cha n g i n g t h e cha r g e - pu m p c u r r e n t i n s o f t w a re. vco bias c u r r e nt v c o b i as c u r r en t m a y b e ad j u st e d usin g b i t s v b 1 t o vb4 in t h e fun c ti o n r e gi s t er . a d di ti o n al b i a s curr e n t will r e d u ce sp uri o us le v e l s, b u t in cr e a s e o v eral l c u r r en t co ns um p t ion in t h e p a r t . a b i a s v a l u e of 0 x 5 shou l d e n su re o s c i l l a t ion a t mo st f r e q u e nc ie s a nd su p p lie s . s e t t i n gs 0x 0, 0x e ,a nd 0x f a r e n o t r e co mm e nde d . s e t t in g 0x3 an d s e t t in g 0x4 a r e r e co mm ended un der m o s t co n d i ti o n s . i m p r o v ed p h a s e n o ise ca n be a c h i ev ed f o r l o w e r bi a s c u r r e n t s . voltage r e gulators ther e a r e tw o b a nd ga p v o l t a g e r e gu la t o rs o n t h e ad f7012 p r o v idin g a s t a b le 2.25 v in t e r n al s u p p l y : a 2.2 f ca p a ci t o r (x5r , np0) t o g r o u n d a t c reg1 and a 470 nf ca p a ci t o r a t c reg2 shou l d b e u s e d to e n su re st ab i l ity . t h e i n te r n a l re fe re nc e en s u r e s co n s is t e n t p e r f o r ma n c e o v er al l s u p p lies a nd r e d u ces t h e c u r r en t co ns um p t io n o f e a ch o f t h e b l o c ks. the com b ina t ion o f r e gu la to rs, b a nd ga p r e fer e n c e, an d b i asin g typ i c a l l y co n s u m e 1.045 ma a t 3.0 v a nd can b e p o w e r e d do wn b y b r in g i n g t h e ce li n e lo w . the s e r i al in t e r f ac e is s u p p lie d b y regu la t o r 1, s o p o w e r i n g do wn th e ce lin e ca u s es t h e co n t en ts o f t h e r e g i st ers to b e los t . the c e line m u s t b e hig h and t h e re g u l a tors m u st b e f u l l y p o we re d on to w r i t e to t h e s e r i a l in t e r f ace . regu l a t o r p o w e r - o n t i me is typ i cal l y 100 s a nd s h o u l d be taken in t o accoun t w h en wr i t in g t o t h e ad f7012 af te r p o we r - up . a l t e r n a t iv ely , re g u l a tor st a t u s m a y b e moni tore d a t t h e mu x o ut p i n o n ce c e h a s been a s s e r t ed , beca use m u x o u t de f a u l t s to t h e re g u l a tor re a d y s i g n a l . o n c e regu la t o r_r e ady is hig h , t h e regu la t o r is p o wer e d u p an d the s e r i a l in t e r f ace i s ac t i ve. fsk m o dul a tio n f s k m o d u l a t i on i s p e r f or me d i n te r n a l ly i n t h e pl l l o op b y swi t chi n g t h e v a l u e o f t h e n r e g i s t er b a s e d o n t h e s t a t us o f t h e txd a t a lin e . th e txd a t a line is s a m p le d a t e a c h c y c l e o f th e pf d bl o c k ( e ve r y 1 / f pf d s e co nds). w h e n tx d a t a ma k e s a lo w- t o -hig h t r a n si t i o n , a n n val u e r e p r es en t i n g t h e de v i a t io n f r e q uen c y is adde d t o t h e n v a l u e r e p r es en t i n g t h e cen t er f r e q u e nc y . i m m e d i a t ely t h e l o o p b e g i ns to l o c k to t h e n e w fr e q u e n c y o f f center + f de v i a t i o n . c o n v ers e ly , w h e n tx d a t a mak e s a hig h -t o - lo w t r a n si t i o n , t h e n v a l u e r e p r es en t i n g t h e de v i a t io n is sub t rac t e d f r o m t h e p ll n val u e rep r es en t i n g t h e cen t er f r e q ue n c y a n d t h e lo o p t r a n si t i o n s t o f ce nter ? f de v i a t i o n .
adf7012 rev. 0 | page 14 of 28 04617-0-026 vco n third-order - ? modulator pfd/ charge pump 4r integer-n fractional-n pa stage ?f dev +f dev txdata fsk deviation frequency f i g u re 30. the d e v i a t ion f r o m t h e ce n t er f r e q uen c y is s e t u s in g b i ts d1 t o d 9 i n th e m o d u la ti o n r e gi s t e r . t h e f r eq ue n c y d e vi a t i o n ma y b e s e t in st eps o f 14 2 ) ( pfd step f hz f = (5) t h e devia t i o n f r eq ue n c y i s t h e r ef o r e 14 2 ) ( number modulation f hz f pfd deviation = (6) w h er e m o du l a t i on n u mb e r is s e t b y b i ts d1 t o d9. t h e m a xim u m da ta ra t e i s a fun c ti o n o f t h e p l l loc k tim e (a n d th e r e q u i r em en t o n fs k s p e c tr um ). b e ca use t h e p l l loc k t i m e i s r e d u ced b y in cr ea si n g t h e loo p - f il t e r ba n d w i d t h, h i g h es t d a t a ra t e s can be ac hiev e d f o r th e wid e r lo o p f i l t er ba n d wid t h s . th e a b s o l u te max i m u m li mi t on lo op f i l t er b a ndwi d t h to ensur e st a b i l i t y fo r a f r ac t i o n a l - n pl l is f pf d /7. f o r a 20 mh z pf d f r eq uen c y , the lo o p ba ndwid t h co u l d b e as hig h as 2.85 mh z. fs k mo d u la t i o n is s e lec t e d b y s e t t in g b i ts s1 and s2 in t h e mo d u l a t i o n re g i ste r l o w . gfsk m o du lation ga us s i a n f r e q uen c y shif t k e y i n g , o r gfs k , r e p r es en ts a f i l t ere d fo r m o f f r e q uenc y shif t k e y i n g . the da t a to b e m o d u l a te d to r f is p r ef i l ter e d di g i t a l l y usin g a n f i ni te im p u ls e r e sp o n s e f i l t er (fir). th e f i l t er ed da t a is t h en us ed t o m o d u la t e t h e sig m a- d e l t a fr a c t i o n a l - n t o g e n e r a t e s p e c t r a l l y - e ffi c i e n t f s k . f s k c o ns i s t s of a s e r i e s of sh ar p t r ans i t i ons i n f r e q u e nc y a s t h e da ta is s w i t ch e d f r o m o n e leve l t o a n o t h e r . th e s h a r p swi t c h ing g e n e ra t e s h i g h er f r eq ue n c y co m p o n en t s a t t h e o u t p u t , r e s u l t in g in a w i der o u t p u t sp e c t r um. w i t h gfs k , t h e s h a r p tra n si tion s a r e r e p l ace d wi th u p t o 128 smal ler s t eps. th e r e s u l t is a g r ad u a l c h a n g e in f r e q uen c y . a s a r e s u l t , t h e h i g h er f r eq ue n c y co m p o n en t s a r e r e d u ced a n d t h e sp e c t r um o c c u pie d is r e d u ce d si g n if ica n t l y . gfsk do es r e q u ir e s o me addi t i o n al desig n w o rk as th e da t a is o n l y s a m p led on ce p e r b i t, an d s o t h e ch o i c e o f cr ys tal is im p o r t a n t t o en s u r e t h e c o r r e c t s a m p l i n g cl o c k i s ge ne r a te d. f o r gfs k a nd go o k , t h e in c o min g b i t s t r e am t o b e tra n s- m i tte d ne e d s to b e s y nch r on i z e d w i t h an o n - c h i p s a m p l i ng clo c k w h ich p r o v ide s o n e s a m p l e p e r b i t t o t h e ga uss i a n fir fi l t e r . t o f a c i l i ta t e t h i s , th e s a m p l i n g c l oc k i s r o u t e d t o th e tx clk pin w h e r e da t a is fetch e d f r o m t h e h o st micr o c o n t r ol ler or m i c r opro c e ss or on t h e f a l l i n g e d ge of t x c l k , an d t h e d a t a i s s a m p l e d a t t h e m i dp oi n t of e a c h bit on t x c l k s r i s i ng e d ge. i n s e r t ing ext e r n al r c lp fs o n txd a t a an d txclk lin e s cr ea t e s sm oo t h er ed g e tra n s i ti o n s a n d im p r o v es s p uri o us p e r f or m a nc e. a s an e x am pl e, su i t abl e c o m p one n t s wou l d b e a 1 kv r e sis t o r a nd 10 nf c a p a ci to r f o r a da ta ra te o f 5 k b ps. fetch sample fetch sample fetch sample fetch adf7012 c i/o int txdata txclk 04617-0-040 f i g u r e 3 1 . tx c l k / tx d a ta s y n c h r o n i z a t i o n . the n u m b er o f s t eps b e tw e e n s y m b ol 0 and s y m b ol 1 is det e r m i n e d b y t h e s e t t in g fo r t h e i n dex co u n t e r . the gf s k de v i a t io n is s e t u p a s 12 m 2 2 ) hz ( = (7) w h er e m is t h e m o d co n t r o l (bi t s mc1 t o mc3 in t h e mo d u l a t i o n re g i ste r ) . the gfs k s a m p lin g c l o c k s a m p les da ta a t t h e da ta ra t e : er indexcount tor dividerfac f bps datarate pfd = ) ( (8) w h er e di v i d e rf a c t o r ca n b e b i ts d1 t o d7, an d in d e x c o u n t e r ca n be b i ts i c 1 a nd i c 2 in t h e m o d u l a tion r e g i s t er . power am plifier the o u t p u t st a g e is b a s e d o n a c l ass e am plif ie r desig n , wi t h an o p en dra i n o u t p u t sw i t ch e d b y t h e v c o sig n al . the o u t p u t c o n t ro l c o ns i s t s of s i x c u r r e n t m i r r or s op e r a t i n g a s a p r og ra mma b l e c u r r en t s o ur ce . t o achie v e maxi m u m v o l t a g e s w i n g, t h e rf ou t p i n n eed s t o be bi a s e d a t d v dd . a s i n g l e p u ll- u p i n d u ct o r t o d v dd en s u r e s a c u r r e n t su p p ly to t h e out p ut st age, p a bias e d to d v dd vol t s, a nd w i t h t h e c o r r e c t choi c e of v a lu e t r ans f or ms t h e i m p e d a nc e. the o u t p u t p o wer ca n b e ad j u s t e d b y cha n g i n g t h e val u e o f b i ts p1 t o p6. t y p i cal l y , this is p 1 t o p6 o u t p u t ?20db m a t 0x0, a nd 13 dbm a t 0x7e a t 868mh z , wi t h t h e o p t i m u m ma t c hin g ne t w or k .
adf7012 rev. 0 | page 15 of 28 the non l i n e a r char ac te r i st ic of t h e ou t p u t st age re su l t s in an output sp e c t r u m c o n t a i n i ng h a r m on i c s of t h e f u n d a me n t a l , es p e c i al l y the thir d an d f i f t h. t o m e e t lo cal r e gu la tion s, a lo w- p a s s f i l t er us ual l y is r e q u ir e d t o f i l t er t h es e ha r m o n ic s. the o u t p u t st a g e ca n b e p o w e r e d do w n b y s e t t i n g bi t pd2 i n t h e f u n c t i o n r e g i s t er lo w . gook mo dulatio n ga us s i a n on-o f f k e yi n g (go o k ) r e p r es en ts a p r ef i l t e r e d fo r m o f o o k m o d u la ti o n . th e us ual l y s h a r p sym b o l tra n si ti o n s a r e r e p l a c e d w i th s m oo th ga u s s i a n - f i l t e r e d t r a n s i t i o n s w i th th e r e su l t b e in g a r e d u c t io n in f r e q uen c y p u l l in g of t h e v c o . f r eq ue n c y p u llin g o f th e v c o in o o k m o d e ca n lead t o a wi der t h a n desi r e d b a n d wi d t h, esp e c i a l ly if i t is n o t p o ssi b l e to in cr eas e t h e lo op f i l t er ba ndwid th t o > 300 kh z. the go o k s a m p lin g c l o c k s a m p les da t a a t t h e da t a ra t e : er indexcount tor dividerfac f bps datarate pfd = ) ( (9) bi ts d1 t o d6 r e p r es en t t h e ou t p u t p o wer fo r th e syst e m fo r a posi ti v e da ta b i t. di v i d e r f a ct o r = 0x3f r e p r es en ts t h e max- im u m p o ss i b le de v i a t io n f r o m p a a t m i ni m u m to p a a t maxim u m o u t p u t . an in dex coun t e r s e t t in g o f 128 is r e co mm e nde d . f i gur e 32 sh o w s t h e s t ep r e s p ons e o f t h e g a us si a n fir f i l t er . an in dex co u n ter o f 16 is dem o n s tra t e d f o r sim p lici ty . w h ile th e p r e- f i l t e r d a ta w o uld swi t c h th e p a d i r e ctl y f r o m o f f t o o n w i th a lo w- t o - h igh d a t a tra n si tio n , t h e f i l t e r e d da ta grad uall y in cr e a s e s t h e p a o u t p u t i n di s c r e t e s t eps. this has t h e ef fe c t o f m aki n g t h e o u t p u t s p ec tr um m o r e co m p a c t . 04617-0-041 pa setting pre-filter data (0 to 1 transition) discretized filter output 16 (max) 15 14 13 12 11 10 9 8 7 5 4 3 2 1 (pa off) 6 f i g u re 32. v a r y i n g p a o u t p ut f o r go o k (index coun ter = 16). a s is t h e cas e w i t h gfs k , go ok r e q u ir es t h e b i t s t r e am ap p l i e d at t x d a t a t o b e s y n c h r o n i z e d w i t h t h e s a mp l i n g c l o c k , t x c l k (see t h e g f s k m o d u l a t i o n sect i o n ) . frequenc (mhz) p o we r (dbm) 10 0 10 20 30 40 50 60 70 80 909.43 910.43 ook gook 910.93 04617-0-043 f i gure 33. go ok v s . o o k f r eq uenc y s p ec tr a (nar r o w - band me asur e m ent) freuenc (mhz) p o we r (dbm) 20 10 0 10 20 30 40 50 60 70 90 80 885.43 910.43 935.93 04617-0-044 gook ook f i gure 34. go ok v s . o o k f r eq uenc y s p ec tr a ( w ideb and m e asu r em ent)
adf7012 rev. 0 | page 16 of 28 outpu t div i der an o u t p u t d i vider is a p r ogra mma b l e divid e r fo llo w in g the v c o in t h e p l l lo o p . i t is us ef u l wh en usin g t h e ad f7012 t o g e n e ra t e f r eq uen c ies o f < 500 mh z. 04617-0-042 pfd cp pa output divider loop filter reference divider n 1/2/4/8 vco f i gure 35. o u tput d i v i de r l o c a ti on in pll. the o u t p u t divider ma y be us e d t o r e d u ce f e e d thr o ug h o f t h e v c o b y a m pl if yin g o n l y t h e v c o/2 com p on e n t, r e s t r i c t in g t h e v c o f eed th r o ugh t o l e ak a g e . b e ca us e t h e divi der is in lo op , t h e n r e g i s t er v a l u es s h o u l d b e s e t u p acco rding t o th e usual f o r m u l a . h o wev e r , th e v c o ga in (k v ) sh o u ld b e s c a l e d acco r d ing to t h e divi der s e t t ing, as sh o w n in t h e fol l o w in g exa m ple . f o u t = 433 mh z, fv co = 866 m h z, k v @ 868 mh z = 60 mh z/v ther efo r e , k v f o r lo o p f i l t er desig n = 30 mh z/v . the di v i der va l u e is s e t i n t h e r r e g i s t er . table 5. o d 1 o d 2 d i v i d e r stat us 0 0 d i v i d e r o f f 0 1 divide by 2 1 0 divide by 4 1 1 divide by 8 muxout m o des the mu x o u t p i n al lo ws t h e u s er acces s t o va r i o u s in t e r n al sig n a l s in t h e t r a n smi t t e r , and pr o v ides info r m a t io n o n t h e p ll lo ck s t a t us, t h e r e gu la t o r , a nd t h e b a t t e r y v o l t a g e . the mux o ut is ac ces s ed b y p r og ra mmin g b i ts m 1 t o m4 in t h e fu n c ti o n r e gi s t er a n d o b se r v i n g th e si gn al a t th e m u x o ut p i n . ba ttery voltage read b a c k b y s e t t in g mux o ut t o 1010 t o 1101, th e ba t t er y v o l t a g e can b e es t i ma t e d . th e b a t t e r y m e asur i n g cir c ui t fe a t ures a v o l t a g e divid e r a nd a com p a r a t o r w h er e t h e divi de d - do w n su p p ly volt age i s c o m p are d to t h e re g u l a tor volt age. table 6. muxout muxout high muxout low 1 0 1 0 d v dd > 3.25 v dv dd < 3.25 v 1 0 1 1 d v dd > 3.0 v dv dd < 3.0 v 1 1 0 0 d v dd > 2.75 v dv dd < 2.75 v 1 1 0 1 d v dd > 2.35 v dv dd < 2.35 v the acc u rac y o f t h e me as ur e m e n t is li mi t e d b y t h e acc u rac y o f t h e regu la t o r v o l t a g e and als o t h e in t e r n al r e sis t o r t o lera n c es. regu l a tor read y the r e gu l a to r h a s a p o w e r - u p t i m e , de p e nda n t o n p r o c ess an d t h e e x te r n a l c a p a c i tor . t h e re g u l a tor re a d y s i g n a l i n d i c a te s t h a t t h e regu la t o r is f u l l y p o w e r e d , and t h a t t h e s e r i al in t e r f ace is ac t i v e . this is t h e defa u l t s e t t i n g o n p o w e r - u p a t mu x o u t . digital lock detect dig i t a l lo c k dete c t in dic a t e s tha t the s t a t us o f t h e p ll lo o p . the p ll lo o p ta k e s tim e t o s e t t le o n p o wer - u p and w h en t h e f r eq uen c y o f th e lo o p is c h a n g e d b y c h an g i n g t h e n val u e . w h en lo ck det e c t is hig h , t h e pfd has co un t e d a n u m b er o f co n s e c u t i v e c y cles w h er e t h e phas e er r o r is < 15 n s . th e lo ck det e c t p r e c isio n b i t in t h e f u n c t i o n r e g i st er d e t e r m in e s w h et h e r this is 3 c y c l es ( l d p = 0), o r 5 c y c l es (ld p =1). i t is r e co m- m e nde d t h a t l d p b e s e t to 1. the lo ck dete c t is n o t com p letely acc u ra t e and g o es hig h b e fo r e t h e o u t p ut has s e t t le d t o exac t l y t h e co r r e c t f r e q uen c y . i n ge n e r a l, ad d 50% to t h e i n di ca te d loc k tim e t o o b t a i n lock tim e t o w i th in 1 kh z . th e lock d e t e ct sig n a l can b e us e d to de ci de w h en t h e p o w e r am plif ier (p a) shou l d b e e n abl e d. r div i d e r m u x o u t prov i d e s t h e output of t h e r d i v i d e r . t h i s i s a na r r o w p u ls e d dig i t a l sig n a l a t f r e q uen c y f pf d . this sig n al ma y b e us e d t o ch e c k t h e o p er a t io n o f t h e cr ys t a l circ ui t and t h e r d i vi der . r di vi der/ 2 i s a b u f f er ed v e r s i o n o f th i s si gn al a t f pfd /2.
adf7012 rev. 0 | page 17 of 28 theory of operation choosing the exter n al inductor value the ad f7012 a l lo ws o p era t ion a t man y dif f er e n t f r eq uen c ies b y cho o s i ng t h e e x te r n a l v c o i n du c t or to g i ve t h e c o r r e c t output f r e q uen c y . f i gu r e 36 sh o w s b o t h t h e m i ni m u m a nd max i m u m f r e q uen c y vs. t h e i n d u c t o r val u e. th e s e a r e m e as ur em e n ts b a s e d o n 0603 cs typ e in d u c t o r s f r o m c o ilcra f t, and a r e in t e n d e d as gui d e l in e s in ch oosi n g th e in d u ct o r beca use boa r d la y o u t a n d ind u c t o r ty p e v a r i es b e tw e e n a p plica t io n s . the i n d u c t o r va l u e sh o u ld b e ch os e n s o i t is b e tw e e n t h e mini m u m an d max i m u m v a l u e. min ( m e a s ) max ( m e a s ) m i n ( eqn) max ( e q n ) inductance (nh) fre q ue ncy (mhz) 1200 1000 900 1100 700 800 500 400 600 300 01 0 51 5 2 0 3 0 25 35 04617-0-031 f i gure 36. o u tput f r equ e nc y v s . e x tern al i n duc t or v a l u e ibias = 2.0 ma. f o r f r eq uen c ies betw een 270 m h z and 550 mh z, i t is r e co mm e nde d to o p er a t e t h e v c o a t t w ic e t h e desir e d o u t p u t f r e q uen c y a n d us e t h e div i de - b y - 2 o p t i o n . this en sur e s r e l i a b l e o p era t ion o v er tem p er a t ur e and s u p p l y . f o r f r eq uen c ies betw een 130 m h z and 270 mh z, i t is r e co mm e nde d to o p er a t e t h e v c o a t fo ur t i m e s t h e desir e d output f r e q u e nc y and u s e t h e d i v i d e - b y - 4 opt i on . f o r f r eq uen c ies b e lo w 130 m h z, i t is bes t t o us e th e divide-b y-8 opt i on . i t i s not ne c e s s ar y to u s e t h e v c o d i v i d e r f o r f r eq uen c ies abo v e 550 mh z. ad i s imp ll is a p ll desig n t o ol which can p e r f o r m t h e f r eq uen c y calc u l a t ion s f o r th e ad f7012, a n d is a v a i la b l e a t ww w . a n a l o g . c o m / p ll . choos ing the crystal/pfd valu e the ch o i ce o f cr ys t a l val u e is an im p o r t an t on e . the p f d f r e q uen c y m u s t b e t h e s a m e as t h e cr ys t a l va l u e o r a n in t e g e r divisio n o f i t . th e p f d de t e r m i n es t h e phas e no is e , s p ur io us le vels an d lo ca t i o n , de v i a t io n f r e q uen c y , and t h e d a t a r a te in t h e c a se o f g f s k . th e f o ll o w i n g sec t i o n s d e sc r i be s o m e fact o r s th a t s h o u ld be co n s id e r ed w h en ch o o s i n g th e cr ys tal v a l u e . stan da rd c r ys tal v a lu es s t a nda rd cr ys tal val u es a r e 3.68 64 mh z, 4 m h z, 4.096 mh z, 4.9152 mh z, 7. 3728 mh z, 9.83 04 mh z, 10 m h z, 11.0592 m h z, 12 mh z, and 14 .4792 mh z. cr ys tals wi t h t h es e val u es a r e u s u a l l y a v ai l a bl e in sto c k and c o st l e ss t h an c r y s t a l s w i t h nons t a n d a rd v a lu e s . reference s p urious levels ref e r e n c e s p ur io us lev e l s (s p u rs) o c c u r a t m u l t i p les o f th e p f d f r e q uen c y . th e r e fer e n c e s p ur clos es t t o t h e ca r r ier is us ual l y h i gh e s t w i th th e s p u r fu rt h e r o u t b e i n g a t t e n u a t e d b y t h e l o o p f i l t er . th e le ve l o f r e f e r e n c e s p u r is lo w e r f o r lo w e r p f d f r e q uen c ies. i n desig n s wi th hig h o u t p u t p o w e r wh er e sp ur io us le v e l s a r e t h e ma in con c er n, a l o w e r p f d f r e q uen c y (<5 mh z) ma y b e desira b l e. beat note s p urs th e s e a r e sp urs o c c u r r i n g fo r v e r y smal l o r v e r y la rg e val u es in t h e f r ac t i o n al re g i s t er . th es e a r e q u ickl y a t t e n u a t e d b y t h e lo o p f i l t er . s e le c t ion o f t h e p f d t h er efo r e det e r m i n e s t h e i r lo ca t i o n , a nd en s u r e s t h a t t h e y ha ve neg l ig i b l e ef fe c t o n t h e t r a n s m i t t e r sp e c t r u m . phase noise the phas e n o is e o f a f r e q uen c y sy n t h e si zer i m pr o v es b y 3db fo r e v er y do ub lin g o f t h e p f d f r e q uen c y . b e c a us e a c p is r e l a t e d to t h e phas e n o is e , t h e p f d ma y b e i n cr e a s e d t o r e d u ce t h e a c p in t h e sys t em. pfd f r e q uen c ies o f < 5mh z typ i cal l y de l i v e r s u f f i cien t phas e n o is e p e r f o r ma n c e fo r m o st sys t em s. de viation f r e q uen c y the d e v i a t ion f r e q uen c y is ad j u st a b le in st eps of 14 2 ) ( pfd step f hz f = ( 1 0 ) t o g e t th e e x a c t d e vi a t i o n f r eq ue n c y r e q u i r ed , en s u r e f st e p is a fac t o r o f t h e des i r e d d e v i a t ion. tips on des i gning the loop filte r the lo o p f i l t er desig n is cr ucial in ens u r i n g s t ab le o p era t io n o f th e tra n sm i t t e r , m e e t i n g a d j a cen t ch a n n e l p o w e r (a c p ) sp e c if ic a t io n s , and m e et i n g sp u r io us r e q u ir em e n ts fo r t h e rel e v a n t re g u l a t i ons . a d i s i m p l l i s a f r e e to o l av ai l a bl e to ai d t h e desig n o f lo o p f i l t ers. th e us er en t e rs t h e desir e d f r e q uen c y r a n g e, t h e r e fer e n c e cr y s t a l and pf d va l u es, and t h e des i r e d loo p ba n d w id th. a d i s i m p l l g i v e s a g ood s t a r tin g po in t f o r th e f i l t er , a nd t h e f i lter ca n b e f u r t her o p t i mi ze d b a s e d o n t h e cr i t er ia be lo w .
adf7012 rev. 0 | page 18 of 28 setting tuning sensitivity value the t u ning s e n s i t ivi t y o r kv is u s ua l l y de n o te d i n mhz/ v a nd is r e q u ir ed f o r th e lo o p f i l t er desig n . i t r e f e rs t o the a m o u n t t h a t a change of a vol t i n t h e vol t age a p pl i e d to v c o in pi n , c h a n g e s th e ou t p u t f r eq uen c y . t y p i c a l da ta f o r the ad f 7012 o v er a f r e q u e nc y r a nge i s sh o w n . frequency (mhz) k v ( m hz/v) 120 100 60 80 40 20 0 200 400 300 600 500 800 900 1000 700 1100 004617-0-032 fi g u r e 3 7 . k v v s . v c o fr e q u e n c y cha r ge-pump cu rrent the cha r g e -p u m p c u r r en t al lo ws t h e lo o p f i l t e r b a n d w i d t h t o b e cha n g e d usin g t h e r e g i st ers. the lo o p b a ndwi d t h r e d u ces as t h e c h a r g e p u m p c u r r en t is r e d u ced a nd vice v e rs a. selecting loop filter b a ndwidth da ta r a t e the lo o p f i l t er b a ndwi d t h sh ou ld us ual l y b e a t tw o t o t h r e e tim e s t h e da ta ra t e . t h i s e n s u r e s th a t t h e p l l ha s a m p l e tim e t o j u m p b e t w een t h e m a rk a n d s p a c e f r eq ue n c ie s . ac p i n t h e cas e w h e r e t h e a c p s p e c if ica t ion s a r e dif f i c u l t t o m e e t , t h e lo o p f i lter b a nd w i d t h ca n b e r e d u ce d f u r t her to r e d u ce t h e phas e n o is e a t t h e ad jace n t channe l . the f i l t er r o l l s o f f a t 20 db p e r de ca de. s p uri o us l e v e ls i n t h e cas e w h e r e t h e o u t p u t p o w e r is q u i t e hig h , a r e d u ce d lo op f i l t er b a ndwi d t h r e d u ces t h e sp u r io us le vels e v e n f u r t h e r , an d p r o v ide s ad di t i o n a l ma rg in o n t h e sp e c if ic a t ion . the fol l o w in g s e c t io n s p r o v ide exa m ples o f lo o p f i l t er desig n s fo r ty p i ca l a p pli c a t io ns i n sp e c if ic f r e q uen c ies. pa ma tchi ng the ad f7012 exhi b i ts o p t i m u m p e r f o r ma n c e in t e r m s o f t r a n smi t p o w e r a nd c u r r en t co nsum p t io n o n ly i f t h e rf o u t p ut p o r t i s prop e r ly ma tc he d to t h e an te n n a i m p e da nc e . zopt_p a de p e n d s p r im a r i l y o n t h e r e q u ir e d ou t p ut p o w e r , a nd t h e f r e q uenc y r a n g e. s e le c t i n g t h e o p t i m u m zop t _p a he l p s t o minimize t h e c u r r en t c o n s um pt io n. this da t a sh e e t c o n t ai ns a n u mb e r of m a tc h i ng ne t w or k s for c o m m o n f r e q u e nc y b a nd s . u n d e r c e r t ai n c o nd i t i o ns i t i s re c o m m e n d e d t o ob t a i n a sui t ab le zop t _p a v a l u e b y m e an s of a lo ad-p u l l me a s u r e m e n t . a ntenn a lpf rf out zopt_pa pa dv dd 04716-0-033 f i g u re 38. a d f7 01 2 w i t h h a r m oni c f i lte r the i m p e dan c e ma t c hin g v a l u es p r o v ide d in t h e n e xt s e c t io n a r e f o r 50 ? en vi r o n m en t s . an ad di ti o n al ma t c hi n g n e t w o r k ma y b e re qu i r e d af te r t h e h a r m oni c f i lte r to ma tch to t h e a n ten n a i m p e dan c e. this ca n b e in co r p o r a t e d i n to t h e f i lter desig n i t s e lf i n o r der to r e d u ce ex ter n a l co m p on e n ts. transmi t protoc ol a n d c o di ng consi d era t io ns 04617-0-034 preamble sync word id field data field crc f i g u re 39. t y pic a l f o r m at of a t r ans m i t p r o t ocol a dc-f r e e p r eam b l e p a t t e r n s u c h as 10101010 is r e co m- m e nde d fo r fs k/ask/o o k d e m o d u l a t i on. pr e a m b l e p a t t e r n s wi th lo n g er r u n-len g th co n s tra i n t s s u ch as 1100 1100. can als o b e us e d . h o w e ver , t h is can r e su l t in a lo n g er sy nchr o n iza t io n t i me of t h e re c e i v e d bit st re a m i n t h e c h o s e n re c e ive r .
adf7012 rev. 0 | page 19 of 28 application examples u1 adf7012 dv dd 1 c reg1 2 cp out 3 txdata 4 txclk 5 c reg2 r set agnd dv dd rf out 24 23 22 21 20 muxout 6 dgnd 7 osc1 8 osc2 9 rf gnd vco in c vco l2 19 18 17 16 clk out 10 clk 11 l1 ce 15 14 data 12 le 13 04617- 0- 035 c reg1 c reg2 txdata txdata txclk txclk clk out clk out muxout clk muxout c6 2.2 f c5 2.2 f c5 100pf c10 470nf l1 l2 c1 c2 c3 r1 r2 v dd c13 2.2 f c12 100pf v dd v dd j1 osc2 osc1 j2 j3?3 clk j4 c7 27pf c8 27pf c15 c14 c9 y1 c11 0.22 f r9 3.6k ? r6 1k ? r7 1k ? r8 1k ? r3 1k ? 9 pin d- t ype pl ug data j3?5 j3?6 j3?8 data r4 1k ? le j3?7 le r5 1k ? l3 ce txdata j5?1 j5?2 txclk muxout j5?3 j5?4 clk out clk j5?5 j5?5 data le j5?7 j5?8 ce v dd j5?9 j5?10 10 pin header (5x2) 1k ? 1k ? 1k ? 1k ? v dd c5+ 10 f lf1 lf2 cf1 cf2 cf2 f i g u re 40. a p pl ic at i o ns d i ag r a ms wit h ha r m on ic f i lte r
adf7012 rev. 0 | page 20 of 28 315 mhz operation the recommendations here are guidelines only. the design should be subject to internal testing prior to fcc site testing. matching components need to be adjusted for board layout. the fcc standard 15.231 regulates operation in the band from 260mhz to 470mhz in the us. this is used generally in the transmission of rf control signals, such as in a satellite- decoder remote control, or remote keyless entry system. the band cannot be used to send any continuous signal. the maximum output power allowed is governed by the duty cycle of the system. a typical design example for a remote control is shown next. design criteria 315 mhz center frequency fsk/ook modulation 1 mw output power house range meets fcc 15.231 the main requirements in the design of this remote are a long battery life and sufficient range. it is possible to adjust the output power of the adf7012 to increase the range depending on the antenna performance. the center frequency is 315 mhz. because the adf7012 vco is not recommended for operation in fundamental mode for frequencies below 400 mhz, the vco needs to operate at 630 mhz. figure 36 (output frequency vs. external inductor value) implies an inductor value of 7.6 nh or close to this. the chip inductor chosen = 7.5 nh (0402cs-7n5 from coilcraft). coil inductors are recommended to provide sufficient q for oscillation. crystal and pfd phase noise requirements are not excessive as the adjacent channel power requirement is ?20 db. the pfd is chosen so as to minimize spurious levels (beat note and reference), and to ensure a quick crystal power-up time. pfd = 3.6864 mhz ? power-up time 1.6ms. figure 10 shows a typical power-on time for a 4 mhz crystal. n-divider the n divider is determined as being: nint = 85 nfrac = (1850)/4096 vco divide-by-2 is enabled deviation the deviation is set to 50 khz so as to accommodate a simple receiver architecture. the modulation steps available are in 3.6864 mhz/2 14 : modulation steps = 225 hz modulation number = 50 khz/225 hz = 222 bias current because low current is desired, a 2.0 ma vco bias can be used. additional bias current reduces any spur, but increases current consumption. the pa bias can be set to 5.5 ma and achieve 0 dbm. loop filter bandwidth the loop filter is designed with adisimpll version 2.5. the loop bandwidth design is straightforward because the 20 db bandwidth is generally of the order of >400 khz (0.25% of center frequency). a loop bandwidth of close to 100 khz strikes a good balance between lock time and spurious suppression. if it is found that pulling of the vco is more than desired in ook mode, the bandwidth could be increased. design of harmonic filter the main requirement of the harmonic filter should ensure that the third harmonic level is < ?41.5 dbm. a fifth-order chebyshev filter is recommended to achieve this, and a suggested starting point is given next. the pi format is chosen to minimize the more expensive inductors. component valuescrystal: 3.6864mhz loop filter i cp 0.866 ma lbw 100 khz c1 680 pf c2 12 nf c3 220 pf r1 1.1 kv r2 3 kv matching l1 56 nh l2 1 nf c14 short c15 open harmonic filter l4 22 nh l5 22 nh cf1 3.3 pf cf2 8.2 pf cf3 3.3 pf
adf7012 rev. 0 | page 21 of 28 433 mhz operation the recommendations here are guidelines only. the design should be subject to internal testing prior to etsi site testing. matching components need to be adjusted for board layout. the etsi standard en 300-220 governs operation in the 433.050 mhz to 434.790 mhz band. for many systems, 10% duty is sufficient for the transmitter to output 10 dbm. design criteria 433.92 mhz center frequency fsk modulation 10 mw output power 200 m range meets etsi 300-220 the main requirement in the design of this remote is a long battery life and sufficient range. it is possible to adjust the output power of the adf7012 to increase the range depending on the antenna performance. the center frequency is 433.92 mhz. it is possible to operate the vco at this frequency. figure 36 shows the inductor value vs. center frequency. the inductor chosen is 22 nh. coilcraft inductors such as 0603-cs-22nxjbu are recommended. crystal and pfd the phase noise requirement is such to ensure the power at the edge of the band is < ?36 dbm. the pfd is chosen so as to minimize spurious levels (beat note and reference), and to ensure a quick crystal power-up time. pfd = 4.9152 mhz ? power-up time 1.6 ms. figure 10 shows a typical power-up time for a 4 mhz crystal. n-divider the n divider is determined as being: nint = 88 nfrac = (1152)/4096 vco divide-by-2 is not enabled deviation the deviation is set to 50 khz so as to accommodate a simple receiver architecture. the modulation steps available are in 4.9152 mhz/2 14 : modulation steps = 300 hz modulation number = 50 khz/300hz = 167 bias current because low current is desired, a 2.0 ma vco bias can be used. additional bias current reduces any spurious, but increases current consumption. the pa bias can be set to 5.5 ma and achieve 10 dbm. loop filter bandwidth the loop filter is designed with adisimpll version 2.5. the loop bandwidth design requires that the channel power be < ?36 dbm at 870 khz from the center. a loop bandwidth of close to 160 khz strikes a good balance between lock time for data rates, including 32 kbps and spurious suppression. if it is found that pulling of the vco is more than desired in ook mode, the bandwidth could be increased. design of harmonic filter the main requirement of the harmonic filter should ensure that the third harmonic level is < ?30 dbm. a fifth-order chebyshev filter is recommended to achieve this, and a suggested starting point is given next. the pi format is chosen to minimize the more expensive inductors. component valuescrystal: 4.9152 mhz loop filter icp 2.0 ma lbw 100 khz c1 680 pf c2 12 nf c3 270 pf r1 910 v r2 3.3 kv matching l1 22 nh l2 10 pf c14 short c15 open harmonic filter l4 22 nh l5 22 nh cf1 3.3 pf cf2 8.2 pf cf3 3.3 pf
adf7012 rev. 0 | page 22 of 28 868 mhz operation the recommendations here are guidelines only. the design should be subject to internal testing prior to etsi site testing. matching components need to be adjusted for board layout. the etsi standard en 300-220 governs operation in the 868 mhz to 870mhz band. the band is broken down into several subbands each having a different duty cycle and output power requirement. narrowband operation is possible in the 50khz channels, but both the output power and data rate are limited by the ?36 dbm adjacent channel power specification. there are many different applications in this band, including remote controls for security, sensor interrogation, metering and home control. design criteria 868.95 mhz center frequency (band 868.7mhz ? 869.2 mhz) fsk modulation 12 dbm output power 300 m range meets etsi 300-220 38.4 kbps data rate the design challenge is to enable the part to operate in this particular subband and meet the acp requirement 250 khz away from the center. the center frequency is 868.95 mhz. it is possible to operate the vco at this frequency. figure 31 shows the inductor value vs. center frequency. the inductor chosen is 1.9 nh. coilcraft inductors such as 0402-cs-1n9xjbu are recommended. crystal and pfd the phase noise requirement is such to ensure the power at the edge of the band is < ?36 dbm. this requires close to ?100 dbc/hz phase noise at the edge of the band. the pfd is chosen so as to minimize spurious levels (beat note and reference), and to ensure a quick crystal power-up time. a pfd of < 6 mhz places the largest pfd spur at a frequency of greater than 862 mhz, and so reduces the requirement on the spur level to ?36 dbm instead of ?54 dbm. pfd = 4.9152 mhz ? power up-time 1.6 ms. figure 10 shows a typical power-on time for a 4mhz crystal. n-divider the n divider is determined as being: nint = 176 nfrac = (3229)/4096 vco divide-by-2 is not enabled. deviation the deviation is set to 19.2 khz so as to accommodate a simple receiver architecture and also ensure that the modulation spectrum is narrow enough to meet the adjacent channel power (acp) requirements. the modulation steps available are in 4.9152 mhz/2 14 : modulation steps = 300 hz modulation number = 19.2 khz/300 hz = 64. bias current because low current is desired, a 2.5 ma vco bias can be used. additional bias current reduces any spurious, but increases current consumption. a 2.5 ma bias current gives the best spurious vs. phase noise trade-off. the pa bias should be set to 7.5 ma to achieve 12 dbm. loop filter bandwidth the loop filter is designed with adisimpll version 2.5. the loop bandwidth design requires that the channel power be < ?36 dbm at 250 khz from the center. a loop bandwidth of close to <60 khz is required to bring the phase noise at the edge of the band sufficiently low to meet the acp specification. this represents a compromise between the data rate requirement and the phase noise requirement. design of harmonic filter the main requirement of the harmonic filter should ensure that the second and third harmonic levels are < ?30 dbm. a fifth- order chebyshev filter is recommended to achieve this, and a suggested starting point is given next. the pi format is chosen to minimize the more expensive inductors. component valuescrystal: 4.9152 mhz loop filter icp 1.44 ma lbw 60 khz c1 1.5 nf c2 22 nf c3 560 pf r1 390 v r2 910 v matching l1 27 nh l2 6.2 nh c14 470 pf c15 open harmonic filter l4 8.2 nh l5 8.2 nh cf1 4.7 pf cf2 6.8 pf cf3 4.7 pf
adf7012 rev. 0 | page 23 of 28 915 mhz operation the recommendations here are guidelines only. the design should be subject to internal testing prior to fcc site testing. matching components need to be adjusted for board layout. fcc 15.247 and fcc 15.249 are the main regulations governing operation in the 902 mhz to 928 mhz band. fcc 15.247 requires some form of spectral spreading. typically, the adf7012 would be used in conjunction with the frequency hopping spread spectrum (fhss) or it may be used in conjunction with the digital modulation standard which requires large deviation frequencies. output power of < 1 w is tolerated on certain spreading conditions. compliance with fcc 15.249 limits the output power to ?1.5 dbm, but does not require spreading. there are many different applications in this band, including remote controls for security, sensor interrogation, metering, and home control. design criteria 915.2mhz center frequency fsk modulation 10 dbm output power 200 m range meets fcc 15.247 38.4 kbps data rate the center frequency is 915.2 mhz. it is possible to operate the vco at this frequency. figure 36 shows the inductor value vs. center frequency. the inductor chosen is 1.6 nh. coilcraft inductors such as 0603-cs-1n6xjbu are recommended. additional hopping frequencies can easily be generated by changing the n value. crystal and pfd the phase noise requirement is such to ensure that the 20 db bandwidth requirements are met. these are dependant on the channel spacing chosen. a typi cal channel spacing would be 400 khz, which would allow 50 channels in 20 mhz and enable the design to avoid the edges of the band. the pfd is chosen so as to minimize spurious levels. there are beat note spurious levels at 910 mhz and 920 mhz, but the level is usually significantly less than the modulation power. they are also attenuated quickly by the loop filter to ensure a quick crystal power-up time. pfd = 10 mhz ? power-up time 1.8 ms (approximately). figure 10 shows a typical power-on time for a 4 mhz crystal. n-divider the n divider is determined as being: nint = 91 nfrac = (2130)/4096 vco divide-by-2 is not enabled deviation the deviation is set to 19.2 khz so as to accommodate a simple receiver architecture, and also to ensure the available spectrum is used efficiently. the modulation steps available are in 10 mhz/2 14 : modulation steps = 610 hz modulation number = 19.2 khz/610 hz = 31. bias current because low current is desired, a 3 ma vco bias can be used and still ensure oscillation at 928 mhz. additional bias current reduces any spurious noise, but increases current consumption. a 3 ma bias current gives the best spurious vs. phase noise trade-off. the pa bias should be set to 5.5 ma to achieve 10 dbm power. loop filter bandwidth the loop filter is designed with adisimpll version 2.5. a data rate of 170 khz is chosen, which allows for data rates of > 38.4 kbps. it also attenuates the beat note spurs quickly to ensure they have no effect on system performance. design of harmonic filter the main requirement of the harmonic filter should ensure that the third harmonic level is < ?41.5 dbm. a fifth-order chebyshev filter is recommended to achieve this, and a suggested starting point is given next. the pi format is chosen to minimize the number of inductors in the system. component valuescrystal: 10 mhz loop filter icp 1.44 ma lbw 170 khz c1 470 pf c2 12 nf c3 120 pf r1 470 v r2 1.8 kv matching l1 27 nh l2 6.2 nh c14 470 pf c15 open harmonic filter l4 8.2 nh l5 8.2 nh cf1 4.7 pf cf2 6.8 pf cf3 4.7 pf
adf7012 rev. 0 | page 24 of 28 register descri ptions r register d1 crystal doubler 0 crystal doubler off 1 crystal doubler on x1 xoeb 0 xtal oscillator on (default) 1 xtal oscillator off od2 od1 output divider 0 disabled 0 divide by 2 1 divide by 4 1 0 1 0 1 divide by 8 va2 va1 vco adjust 0 no vco adjustment 0( f center ? ( 1 f)) 1( f center ? ( 2 f)) 1 0 1 0 1( f center ? ( 3 f)) cl4 cl3 cl2 cl1 clk out divide ratio 0 2 0 0 0 . . 1 1 0 1 0 . . 0 4 6 8 . . 0 1 1 0 . . 0 0 0 1 . . . 16 (default) . . . 1 28 11 1 1 1 30 rl4 rl3 rl2 rl1 rf r counter divide ratio 0 1 0 0 0 . . . 1 0 1 0 . . . 2 3 4 . . 0 1 1 0 . . 0 0 0 1 . . . . 10 . 0 1 12 11 0 1 13 10 1 1 14 11 1 1 15 addre s s bits 11-bit frequency error correction 4-bit r divider clock out divider vco adjust output divider xoeb cry s t al double r va 1 od2 od1 va 2 cl4 f7 f8 f9 f10 r3 r4 d1 cl1 cl2 cl3 x1 f11 r1 r2 f6 f5 c2 (0 ) c1 (0 ) f1 f2 f3 f4 db1 6 db1 5 db1 4 db1 7 db2 0 db1 9 db1 8 db2 1 db1 3 db1 2 db1 1 db1 0 db9 db8 db7 db6 db5 db4 db2 2 db2 3 db2 4 db2 6 db2 7 db2 8 db2 5 db1 db0 db2 db3 db2 9 db3 0 db3 1 04617-0-027 f-counter offset +1023 +1022 . +1 +0 ?1 ?0 ?1 ?1023 ?1024 f11 0 0 0 0 0 1 1 . 1 1 e.g., f-counter offset = 1, fractional offset = 1/2 15 ....... ... .... ....... ....... ....... ....... ....... ....... ....... ....... ....... f3 1 1 . 0 0 1 1 . 0 0 f2 0 0 . 0 0 1 1 . 0 0 f1 0 1 . 1 0 1 0 . 1 0 f i g u re 41.
adf7012 rev. 0 | page 25 of 28 n-cou n ter latch p1 prescaler 0 4/5 1 8/9 the n-value chosen is a minimum of p 2 + 3p + 3. for prescaler 8/9 this means a minimum n-divide of 91. n4 n3 n2 n1 n-counter divide ratio 0 1 0 0 . . . 1 0 1 0 . . . 0 2 3 . . . 0 0 1 . . . 0 0 0 . . . 1 254 11 1 1 1 n7 n6 n5 0 0 0 . . . 1 0 0 0 . . . 0 0 0 . . . 1 1 1 1 1 n8 0 0 0 . . . 1 1 255 addre s s bits 12-bit fractional-n 8-bit integer-n pr esc a l er p1 m7 m8 m9 m1 0 n2 n3 n5 n6 n7 n8 n4 m1 1 m1 2 n1 m6 m5 c2 (0 ) c1 (1 ) m1 m2 m3 m4 db1 6 db1 5 db1 4 db1 7 db2 0 db1 9 db1 8 db2 1 db1 3 db1 2 db1 1 db1 0 db9 db8 db7 db6 db5 db4 db2 2 db2 3 db1 db0 db2 db3 04617-0-028 modulus divide ratio 0 1 2 . . . 4092 4093 4094 4095 m10 0 0 0 . . . 1 1 1 1 e.g., setting f = 0 in fsk mode turns on the - ? while the pll is an integer value e.g., modulus divide ratio = 2048 - > 1/2 ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... m3 0 0 0 . . . 1 1 1 1 m2 0 0 1 . . . 0 0 1 1 m1 0 1 0 . . . 0 1 0 1 m12 0 0 0 . . . 1 1 1 1 m11 0 0 0 . . . 1 1 1 1 f i g u re 42.
adf7012 rev. 0 | page 26 of 28 modulation registe r g1 gaussian ook must be low 0o n 1 off .p 2 p 1 . pa off . . . . . 1 x 1 0 1 . . 1 ?16.0dbm 1/31 * 14dbm 2/31 * 14dbm . . x 0 1 1 . . 13dbm 1 p6 . . . . . . . 0 0 0 0 . . 11 power amplifier output level .d 2 d 1 . pa off . . . . . 1 x 0 1 0 . . 1 ?16.0dbm 1/31 * 14dbm 2/31 * 14dbm . . x 0 0 1 . . 14dbm 1 d6 . . . . . . . 0 . 0 0 . . 11 if amplitude shift keying selected, txdata = 0 d3 d2 d1 f deviation 0 pll mode 0 0 0 . 1 0 1 0 1 . . 1 ?f step 2 ?f step 3 ?f step ....... 511 ?f step 0 0 1 1 . 1 d9 ....... ....... ....... ....... ....... ....... ....... 0 0 0 0 . 1 if frequency shift keying selected f step = f pfd /2 14 if gaussian frequency shift keying selected addre s s bits mo d control inde x counte r gook power amplifier modulation deviation test bits gfsk mod control mc3 p4 p5 p6 d1 d5 d6 d8 d9 mc1 mc2 ic1 ic2 d7 d2 d3 d4 p3 p2 c2 (1 ) c1 (0 ) s1 s2 g1 p1 db1 6 db1 5 db1 4 db1 7 db2 0 db1 9 db1 8 db2 1 db1 3 db1 2 db1 1 db1 0 db9 db8 db7 db6 db5 db4 db2 2 db2 3 db2 4 db2 6 db2 7 db2 8 db2 5 db1 db0 db2 db3 db2 9 db3 0 db3 1 04617-0-029 s2 s1 modulation scheme 0 fsk 0 gfsk 1 ask 1 0 1 0 1 ook d7 d3 d2 d1 divider factor 0 0 0 0 00 1 0 13 1 2 0 0 1 1 0 0 0 0 . 1... ....... ....... ....... ....... ....... ....... ....... . 1 ....... 127 . 1 . 1 mc3 mc2 mc1 gfsk mod control 0 0 00 11 0 0 . 1 . 1 . 7 . 1 ic2 ic1 index counter 0 0 1 1 01 6 1 0 1 128 32 64 f i g u re 43.
adf7012 rev. 0 | page 27 of 28 func tio n r e gister i1 data invert 0 data 1 data pd3 clk out 0 clk out off 1 clk out on pd2 pa enable 0 p a off 1p a o n cp4 bleed down 0 bleed off 1 bleed on vd1 vco disable 0 vco on 1 vco off cp3 bleed up 0 bleed off 1 bleed on pd1 pll enable 0 pll off 1 pll on cp2 cp1 charge pump current 0 0.3ma 0 0.9ma 1 1.5ma 1 0 1 0 1 2.1ma m4 m3 m2 m1 muxout 0 logic low 0 0 0 0 0 0 0 1 0 1 0 1 0 logic high invalid mode ? do not use regulator ready (default) digital lock detect analog lock detect 0 0 1 1 0 0 0 0 0 0 1 1 1 r divider/2 output 01 1 1 1 n divider/2 output 10 0 0 rf r divider output 11 0 0 data rate 10 1 0 battery measure is > 3.25v 11 1 0 battery measure is > 3v 10 0 1 battery measure is > 2.75v 11 0 1 battery measure is > 2.35v 10 1 1 normal test modes 11 1 1 - ? test modes vb4 vb3 vb2 vb1 vco bias current 0 0.5ma 0 . 1 1 0 . 1 1ma . 8ma 0 1 . 1 0 0 . 1 pa3 pa2 pa1 pa bias 5 a 0 1 0 . 6 a 7 a . 0 0 1 . 0 0 0 . . 1 . 12 a . 1 . 1 addre s s bits charge pump bl e e d cu rre nt muxout pa bias vco bias pll test modes sd test modes ld pr ec ision p ll e nable pa e nable clkout e nable data in ver t vc o dis able pt1 pt4 pt5 st1 st2 st3 st4 pt3 pt2 pa 3 cp 3 cp 4 vd 1 m1 ld1 vb 1 vb 3 vb 4 pa 1 pa 2 vb 2 m2 m3 m4 cp 2 cp 1 c2 (1 ) c1 (1 ) pd 1 pd 2 pd 3 i1 db1 6 db1 5 db1 4 db1 7 db2 0 db1 9 db1 8 db2 1 db1 3 db1 2 db1 1 db1 0 db9 db8 db7 db6 db5 db4 db2 2 db2 3 db2 4 db2 6 db2 7 db2 8 db2 5 db1 db0 db2 db3 db2 9 db3 0 db3 1 04617-0-030 f i g u re 44.
adf7012 rev. 0 | page 28 of 28 outline dimensions 24 13 12 1 6.40 bsc 4.50 4.40 4.30 pin 1 7.90 7.80 7.70 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 seating plane 0.10 coplanarity compliant to jedec standards mo-153ad f i gure 45. 2 4 -l ead thin shr i nk s m a l l o u tline p a ckage [ t ssop ] (ru - 24) ordering guide model temperature r a nge package descri ption package option frequency r a nge adf7012bru ? 40c to +85c tssop ru-24 50 mhz to 1 gh z adf7012bru-r eel ? 40c to +85c tssop, 13ree l ru-24 50 mhz to 1 gh z adf7012bru-r eel7 ? 40c to +85c tssop, 7 ree l ru-24 50 mhz to 1 gh z eval-adf7012 e b 1 evaluation boar d 902 mhz to 928 mhz eval-adf7012 e b 2 evaluation boar d 860 mhz to 880 mhz eval-adf7012 e b 3 evaluation boar d 418 mhz to 435 mhz eval-adf7012 e b 4 evaluation boar d 310 mhz to 330 mhz eval-adf7012 e b 5 evaluation boar d 50 mhz to 1 gh z ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . d04617C0C 10/04(0)

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